1. Field of the Invention
The present invention relates to a core substrate, a manufacturing method thereof, and a structure for a metal via, and more particularly, to a core substrate with a metal via having a new structure, which has no need to process a clearance area and two kinds of holes, that is, a through hole and a buried via hole in a metal layer when manufacturing a core substrate, a manufacturing method thereof, and a structure for a metal via.
2. Description of the Related Art
In line with miniaturization, densification, and thinning of electronic components, studies on thinning and high functions of semiconductor package substrates are in active progress. In recent times, heat generation is becoming a serious problem due to an increase in operation speed according to high performance of chips. The most common method to meet these requirements is a technique of manufacturing a metal core substrate by inserting metal such as copper (Cu), aluminum (Al), or invar having high thermal conductivity in a core of a substrate. In case of such metal, since it has very excellent thermal expansion and thermal conductivity characteristics, it is possible to suppress thermal expansion behavior of the substrate and perform a heat radiation function at the same time.
FIGS. 3a to 3j schematically show each step of a conventional method for manufacturing a core substrate, FIG. 4a shows a through hole of a core substrate manufactured according to the conventional manufacturing method, and FIG. 4b schematically shows a buried via of the core substrate manufactured according to the conventional manufacturing method.
In the prior art, in order to improve performance of thermal conductivity, it is required to form a thermal via hole 53 connected to a metal layer 10 or a ground layer inserted as an intermediate layer of a core substrate. In this case, a process of forming the thermal via hole 53 connected to the ground layer and a process of forming a through hole 51 having an electrical signal of connecting upper and lower parts of the substrate are performed separately. Further, since the holes have different shapes, a SEAM void 51a or a dimple 53a occurs during plating and becomes more serious when a thickness of the core layer 10 is increased.
Describing the conventional process of manufacturing a core substrate, when applying copper (Cu) as the metal layer 10 of FIG. 3a, as shown in FIG. 3b, the metal layer 10 and an insulator 30a are attached through primary lamination. At this time, a copper foil layer 40 may be attached to an outer side of the insulator 30a, and photoresist 20 may be attached onto the metal layer 10 to form a clearance for processing a through hole 50a. When forming the hole 53 having connection with the metal layer 10′ and the hole 51 without connection with the metal layer 10′, since the hole 51 having electrical connection is not connected to the metal layer 10′, it is required to form a clearance. Due to this, a resist pattern 20 is formed by exposing the photoresist 20 on the metal layer 10 in FIG. 3c, and a clearance area is formed using a drill or etching in FIG. 3d. A metal layer pattern 10′ is formed according to the formation of the clearance area. After that, after performing black oxide or brown oxide treatment as in FIG. 3e, a copper clad laminate CCL having a three-layer substrate structure, which has a metal core 10′, is manufactured by laminating and pressing an insulation layer 30b and the copper foil 40.
Further, as in FIG. 3f, when processing the through hole 50a having electrical connection for interlayer connection, the hole 50a is formed by CNC processing or direct CO2 processing. Further, as in FIG. 3h, since the hole 50b connected to the metal core layer 10′ due to heat radiation characteristics has difficulty in CNC processing or direct CO2 processing due to the metal core layer 10′, general CO2 processing is used to make a buried via hole (BVH) type hole. As shown in FIG. 3i, in case of filling plating for the hole after processing the hole, since the holes have two kinds of shapes, that is, the through hole 51 and the BVH 53, it is not easy to set plating conditions, and when performing pattern plating, it is difficult to proceed a process in stack type.
That is, in case of using the conventional method, when forming the hole 53 connected to the metal core layer 10′ and the hole 51 unconnected to the metal core layer 10′, it is difficult to design the hole 53 connected to the metal core layer 10′ or the number of processes is increased due to two kinds of processing and thus process time is also increased.
Further, as shown in FIGS. 4a and 4b, since the through hole 51 and the BVH 53 should be plated at the same time, plating failures such as the SEAM void 51a and the dimple 53a may occur.